FPD1050 Datasheet | Filtronic

FEATURES - 28.5 d Bm Linear Output Power at 12 GHz - 11 d B Power Gain at 12 GHz - 14 d B Maximum Stable Gain at 12 GHz - 41 d Bm Output IP3 - 45% Power-Added Efficiency SOURCE BOND PAD (2x) DRAIN BOND PAD (2X) GATE BOND PAD (1X) DIE SIZE: 470 x 440 µm DIE THICKNESS: 100 µm BONDING PADS: >85 x 60 µm - DESCRIPTION AND APPLICATIONS The FPD1050 is an Al Ga As/In Ga As pseudomorphic High Electron Mobility Transistor (p HEMT), featuring a 0.25 µm by 1050 µm Schottky barrier gate, defined by high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance. The epitaxial structure and processing have been optimized for reliable high-power applications. The FPD750 also features Si3N4 passivation and is also available in a low cost plastic SOT89 plastic package. Typical applications include mercial and other narrowband and broadband high-performance amplifiers, including SAT uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters. - ELECTRICAL SPECIFICATIONS AT 22°C Parameter Power at 1d B Gain pression Maximum Stable Gain (S21/S12) Power Gain at P1d B Power-Added Efficiency Output Third-Order Intercept Point (from 15 to 5 d B below P1d B) Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistivity (see Notes) Phone: +1 408 850-5790 Fax: +1 408 850-5766 Symbol P1d B MSG G1d B PAE IP3 Test Conditions VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS; POUT = P1d B VDS = 10V; IDS = 50% IDSS Matched for optimal power Tuned for best IP3 Min 27.5 10.0 Typ 28.5 14.0 11.0 45 Max Units d Bm d B d B % RF SPECIFICATIONS MEASURED AT f = 12 GHz USING CW SIGNAL 39 41 250 315 520 280 15 1.0 16 16 18 18 45 375 d Bm IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD|...