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9FGL06 - 6-output 3.3V PCIe Clock Generator

Datasheet Summary

Description

The 9FGL06 devices are 3.3V members of IDT's 3.3V Full-Featured PCIe family.

The devices have 6 output enables for clock management and support 2 different spread spectrum levels in addition to spread off.

Features

  • 6.
  • 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs.
  • 9FGL0641 default ZOUT = 100.
  • 9FGL0651 default ZOUT = 85.
  • 9FGL06P1 factory programmable defaults.
  • 1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL) support.
  • Easy AC-coupling to other logic families, see IDT.

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Datasheet preview – 9FGL06

Datasheet Details

Part number 9FGL06
Manufacturer IDT
File Size 319.76 KB
Description 6-output 3.3V PCIe Clock Generator
Datasheet download datasheet 9FGL06 Datasheet
Additional preview pages of the 9FGL06 datasheet.

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Full PDF Text Transcription

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6-output 3.3V PCIe Clock Generator 9FGL06 DATASHEET Description The 9FGL06 devices are 3.3V members of IDT's 3.3V Full-Featured PCIe family. The devices have 6 output enables for clock management and support 2 different spread spectrum levels in addition to spread off. The 9FGL06 supports PCIe Gen1-4 Common Clocked architectures (CC) and PCIe Separate Reference no-Spread (SRnS) and Separate Reference Independent Spread (SRIS) clocking architectures. The 9FGL06P1 can be programmed with a user-defined power up default SMBus configuration.
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