9FGL08 Key Features
- 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
- 9FGL0841 default ZOUT = 100
- 9FGL0851 default ZOUT = 85
- 9FGL08P1 factory programmable defaults
- 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
- Easy AC-coupling to other logic families, see IDT
