z
D = Drain
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Silicon chip on Direct-Copper-Bond substrate - High power dissipation - Isolated mounting surface - 2500V electrical isolation Low drain to tab capacitance(.
Full PDF Text Transcription for IXFC13N50 (Reference)
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IXFC13N50. For precise diagrams, and layout, please refer to the original PDF.
ADVANCED TECHNICAL INFORMATION HiPerFETTM MOSFET ISOPLUS220TM Electrically Isolated Back Surface N-Channel Enhancement Mode High dv/dt, Low trr, HDMOSTM Family IXFC13N50 ...
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hannel Enhancement Mode High dv/dt, Low trr, HDMOSTM Family IXFC13N50 VDSS ID25 RDS(on) trr = 500 = 12 = 0.4 ≤ 250 V A Ω ns ISOPLUS 220TM Symbol VDSS VDGR VGS VGSM ID25 IDM IAR EAR dv/dt PD TJ TJM Tstg TL Weight 1.6 mm (0.062 in.) from case for 10 s Test Conditions TJ = 25°C to 150°C TJ = 25°C to 150°C; RGS = 1 MΩ Continuous Transient TC = 25°C TC = 25°C, pulse width limited by TJM TC = 25°C TC = 25°C IS ≤ IDM, di/dt ≤ 100 A/µs, VDD ≤ VDSS, TJ ≤ 150°C, RG = 2 Ω TC = 25°C Maximum Ratings 500 500 ± 20 ± 30 12 48 13 18 5 140 -55 ... +150 150 -55 ...