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GAL26CLV12 Datasheet PDF

Lattice Semiconductor GAL26CLV12

Low Voltage E2CMOS PLD Generic Array Logic

Part No. GAL26CLV12
Datasheet GAL26CLV12 Download
Manufacturer
Lattice Semiconductor
Description Low Voltage E2CMOS PLD Generic Array Logic
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GAL26CLV12 datasheet page 1 preview

FEATURES

FEATURES

● HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 200 MHz — 3.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology
● 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Standard — Inputs and I/O Interface with Standard 5V TTL Devices
● ACTIVE PULL-UPS ON ALL PINS
● E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention
● TWELVE OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity
● PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability
●

APPLICATIONS

INCLUDE: — Glue Logic for 3.3V Systems — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade
● ELECTRONIC SIGNATURE FOR IDENTIFICATION I Functional Block Diagram I/CLK RESET INPUT 8 I 8 I 8 I 8 I OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q P...
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