GAL26CLV12 Overview
The GAL26CLV12D, at 5 ns maximum propagation delay time, provides higher performance than its 5V counterpart. The GAL26CLV12D can interface with both 3.3V and 5V signal levels. The GAL26CLV12D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which bines CMOS with Electrically Erasable (E2) floating gate technology.
GAL26CLV12 Key Features
- HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 5 ns Maximum Propagation Delay
- Fmax = 200 MHz
- 3.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
- 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE
- JEDEC-patible 3.3V Interface Standard
- Inputs and I/O Interface with Standard 5V TTL Devices
- ACTIVE PULL-UPS ON ALL PINS
- E2 CELL TECHNOLOGY
GAL26CLV12 Applications
- Glue Logic for 3.3V Systems