SY100S355 Datasheet | Micrel Semiconductor

Micrel, Inc. NOT REMENDED FOR NEW DESIGNS QUAD MULTIPLEXER/LATCH Features DESCRIPTION s Max. propagation delay of 1100ps s Max. enable to output delay of 1400ps s IEE min. of - 80m A s Industry standard 100K ECL levels s Extended supply voltage option: VEE = - 4.2V to - 5.5V s Voltage and temperature pensation for improved noise immunity s Internal 75kΩ input pull-down resistors s 50% faster than Fairchild s Function and pinout patible with Fairchild F100K s Available in 28-pin PLCC package The SY100S355 offers four transparent latches with differential outputs and is designed for use in highperformance ECL systems. The Select inputs (S0, S1) select one of the two sources of input data (D0 or D1) to the latch. The Select inputs can also force the outputs to a logic LOW when the latch is in the transparent mode. The latches are in the transparent mode when both Enables (E1, E2) are at a logic LOW state. In the transparent mode, the Select inputs can pass an input logic HIGH from D0 or D1 to the output. If the Select inputs are tied together, then input data from either D0 or D1 is always passed through. A rising edge on either Enable input will latch the outputs with the most recent data at the latch inputs being stored. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75kΩ pull-down resistors. BLOCK DIAGRAM S0 S1 D0a Qa D1a E CD Qa D0b Qb D1b E CD Qb D0c Qc D1c E...