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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM69D536/D
32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM
The MCM69D536 is a 1M–bit static random access memory, organized as 32K words of 36 bits. It features common data input and data output buffers and incorporates input and output registers on–board with high speed SRAM. The MCM69D536 allows the user to concurrently perform reads, writes, or pass–through cycles in combination on the two data ports. The two address ports (AX, AY) determine the read or write locations for their respective data ports (DQX, DQY). The synchronous design allows for precise cycle control with the use of an external single clock (K). All signal pins except output enables (GX, GY) are registered on the rising edge of clock (K).
MCM69D536 Datasheet
