Datasheet4U Logo Datasheet4U.com

MCM72F6 - 512KB and 1MB Synchronous Fast Static RAM Module

General Description

Pin Locations 62, 64, 65, 67, 68, 70, 71, 72, 145, 146, 148, 149, 151, 152, 154, 155 156 15, 31, 44, 86, 92, 105, 121, 134 2, 3, 5, 6, 8, 9, 11, 12, 14, 17, 18, 20, 21, 23, 24, 26, 27, 32, 34, 35, 37, 38, 40, 41, 43, 46, 47, 49, 50, 52, 53, 55, 56, 87, 89, 90, 93, 95, 96, 98, 99, 101, 102, 104, 107

Key Features

  • F7DG10 MCM72F7DG912 MCM72F6DG9 MCM72F6DG10/12 MCM72F7DG9 MCM72F7DG10/12 Symbol IDDA Min.
  • Max 900 860 840 1800 1720 1680 440 400 380 880 800 760 160 140 320 280 Unit mA CMOS Standby Supply Current (Deselected, Clock (K) Cycle Time ≥ tKHKH, All Inputs Toggling at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD.
  • 0.2 V) ISB1.
  • mA Clock Running Supply Current (Deselected, Clock (K) Cycle Time ≥ tKHKH, All Other Inputs Held to Static CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MCM03P02A P-Channel MOSFET MCC
MCM1206 P-Channel MOSFET MCC
MCM1208 P-Channel MOSFET MCC
MCM1216 P-Channel MOSFET MCC
MCM1216A P-CHANNEL MOSFET MCC

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MCM72F10 8MB Synchronous Fast Static RAM Module
MCM72F7 512KB and 1MB Synchronous Fast Static RAM Module
MCM72F8 2MB and 4MB Synchronous Fast Static RAM Module
MCM72F9 2MB and 4MB Synchronous Fast Static RAM Module
MCM72FB8ML 256K x 72 Bit Burst RAM Multichip Module

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM72F6/D 512KB and 1MB Synchronous Fast Static RAM Module The MCM72F6 (512KB) is configured as 64K x 72 bits and the MCM72F7 (1MB) is configured as 128K x 72 bits. Both are packaged in a 168–pin dual– in–line memory module DIMM. Each module uses Motorola’s 3.3 V 64K x 18 bit flow–through BurstRAMs. Address (A), data inputs (DQ, DP), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers. Write cycles are internally self–timed and initiated by the rising edge of the clock (K) input. This feature provides increased timing flexibility for incoming signals. Synchronous byte write (W) allows writes to either individual bytes or to both bytes.