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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM72F6/D
512KB and 1MB Synchronous Fast Static RAM Module
The MCM72F6 (512KB) is configured as 64K x 72 bits and the MCM72F7 (1MB) is configured as 128K x 72 bits. Both are packaged in a 168–pin dual– in–line memory module DIMM. Each module uses Motorola’s 3.3 V 64K x 18 bit flow–through BurstRAMs. Address (A), data inputs (DQ, DP), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers. Write cycles are internally self–timed and initiated by the rising edge of the clock (K) input. This feature provides increased timing flexibility for incoming signals. Synchronous byte write (W) allows writes to either individual bytes or to both bytes.
MCM72F6 Datasheet
