74LVC86 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS 74LVC86 Quad 2-input EXCLUSIVE-OR gate Product specification Supersedes data of February 1996 IC24 Data Handbook 1997 Mar 18 Philips Semiconductors Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate Features - Wide supply voltage range of 1.2 to 3.6 V - In accordance with JEDEC standard no. 8-1A. - Inputs accept voltages up to 5.5 V - CMOS low power consumption - Direct interface with TTL levels QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL t PHL t PLH CI CPD PARAMETER Propagation delay n A, n B to n Y Input capacitance Power dissipation capacitance per gate DESCRIPTION The 74LVC86 is a high-performance, low-power, low-voltage Si-gate CMOS device that is pin and superior to most advanced CMOS patible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC86 provides the 2-input EXCLUSIVE-OR function. CONDITIONS CL = 15 p F; VCC = 3.3 V VCC = 3.3 V, VI = GND to VCC1 TYPICAL 3.7 5.0 55 UNIT ns p F p F NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi )Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in p F; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE - 40°C to +85°C - 40°C to +85°C - 40°C to +85°C - 40°C to +85°C OUTSIDE NORTH AMERICA 74LVC86 N 74LVC86 D 74LVC86 DB 74LVC86 PW NORTH AMERICA 74LVC86 N 74LVC86 D 74LVC86 DB 74LVC86PW DH PKG. DWG. # SOT27-1 SOT108-1 SOT337-1 SOT402-1 PIN CONFIGURATION 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4B 4A 4Y 3B 3A 3Y LOGIC SYMBOL...