BSP110 Datasheet | NXP Semiconductors

DISCRETE SEMICONDUCTORS DATA SHEET BSP110 N-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor DESCRIPTION N-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and designed for use in telephone ringer circuits and for application in relay, high-speed and line transformer drivers. Features - Direct interface to C-MOS, TTL, etc. - High-speed switching - No secondary breakdown PINNING - SOT223 1 = gate 2 = drain 3 = source 4 = drain MARKING CODE BSP110 PIN CONFIGURATION QUICK REFERENCE DATA Drain-source voltage Drain source voltage (non-repetitive peak; tp ≤ 2 ms) Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 °C Drain-source ON-resistance ID = 200 m A; VGS = 10 V Transfer admittance ID = 200 m A; VDS = 15 V  Yfs  min. typ. RDS(on) VDS(SM) ± VGSO ID Ptot VDS BSP110 max. max. max. max. max. typ. max. 80 V 100 V 20 V 325 m A 1.5 W 4.5 Ω 7 Ω 75 m S 150 m S handbook, halfpage 4 d g 1 Top view MAM054 s Fig.1 Simplfied outline and symbol. April 1995 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Drain-source voltage (non-repetitive peak; tp ≤ 2 ms) Gate-source voltage (open drain) Drain current (DC) Drain current (peak) Total power dissipation up to Tamb = 25 °C (note 1) Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient (note 1) Note Rth j-a = VDS(SM) ± VGSO ID IDM Ptot Tstg Tj max. max. max. max. max. max. VDS max. 80 V 100 V 20 V 325 m A 650 m A 1.5 W 150 °C - 65 to + 150 °C 83.3 K/W 1. Device mounted on an epoxy printed-circuit board 40 mm × 40 mm × 1.5 mm; mounting pad for the drain lead min. 6 cm2....