PHD97NQ03LT Datasheet | NXP Semiconductors

N-channel Trench MOS logic level FET Rev. 01 - 24 March 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using Trench MOS technology. This product is designed and qualified for use in puting, munications, consumer and industrial applications only. 1.2 Features and benefits - Fast switching - Lead-free packing - Logic level threshold - Low on-state resistance - Suitable for high frequency applications due to fast switching characteristics 1.3 Applications - puter motherboard high frequency DC-to-DC convertors - Switched-mode power supplies - Voltage regulators 1.4 Quick reference data Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 °C; VGS = 10 V; see Figure 1; see Figure 3 Tmb = 25 °C; see Figure 2 Min Typ Max 25 75 107 Unit V A W drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C drain current total power dissipation gate-drain charge Symbol Parameter Dynamic characteristics QGD VGS = 4.5 V; ID = 25 A; VDS = 12 V; see Figure 9; see Figure 10 VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 7; see Figure 8 1.9 n C Static characteristics RDSon drain-source on-state resistance 5.3 6.3 mΩ NXP Semiconductors N-channel Trench MOS logic level FET 2. Pinning information Table 2. Pin 1 2 3 mb Pinning information Symbol G D S D Description gate drain source mounting base; connected to drain 2 1 3 mb Simplified outline Graphic symbol G mbb076 SOT428 (SC-63; DPAK) 3. Ordering...