NBSG72A Description
1 2 Name VTD0 D0 I/O − LVDS, CML, ECL, LVTTL, LVCMOS Input LVDS, CML, ECL, LVTTL, LVCMOS Input LVECL, LVCMOS Input − Inverted Differential Input 0. Description mon Internal 50 W Termination Pin for D0 and D0 Input. (Note 1) 3 D0 Noninverted Differential Input.
NBSG72A Key Features
- Single-Ended LVECL or LVCMOS/LVTTL Select Inputs
- © Semiconductor ponents Industries, LLC, 2006
- Rev. 5
- LVDS, CML, ECL, LVTTL, LVCMOS Input LVDS, CML, ECL, LVTTL, LVCMOS Input LVECL, LVCMOS Input
- Inverted Differential Input 0. Description mon Internal 50 W Termination Pin for D0 and D0 Input. See Table 4. (Note 1)
- VCC OLS (Note 2) Q0 Q0 VCC EP
- LVECL, LVCMOS Input RSECL Output RSECL Output
- Input RSECL Output RSECL Output