DESCRIPTION
PIN CONFIGURATION (D-PAK) TO-252 FEATURE l -60V/-10.0A, RDS(ON) = 70mΩ(Typ.) @VGS = -10V l -60V/-5.0A, RDS(ON) = 80mΩ(Typ.) @VGS = -10V l Super high density cell design for extremely low RDS(ON) l Exceptional on-resistance and maximum DC current capability l TO-252package design PART MARKING STP605D FXGA F:Year Code X:Date Code Q:Process Code A:Wafer Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA . STP607D 2010. V1 STP605D P Channel Enhancement Mode MOSFET -15.0A ABSOULTE MAXIMUM RATINGS
(Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage VDSS -60 Gate-Source Voltage Continuous Drain Current (TJ=150℃) Pulsed Drain Current TA=25℃ TA=100℃ VGSS ID IDM ±20 -15.0 -7.0 -30 Continuous Source Current (Diode Conduction) IS -15 Power Dissipation TA=25℃ PD 25 Operation Junction Temperature TJ 150 Storgae Temperature Range TSTG -55/150 Thermal Resistance-Junction to Ambient RθJA 25 Unit V V A A A W ℃ ℃ ℃/W STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA .