K4H560838F-UCCC Key Features
- 200MHz Clock, 400Mbps data rate
- VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
- Double-data-rate architecture; two data transfers per clock cycle
- Bidirectional data strobe(DQS)
- Four banks operation
- Differential clock inputs(CK and CK)
- DLL aligns DQ and DQS transition with CK transition
- MRS cycle with address key programs -. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333 -. Burst length (2, 4,
- All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
- Data I/O transactions on both edges of data strobe
