Datasheet4U Logo Datasheet4U.com

K4S160822D - 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL

General Description

The K4S160822D is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 1,048,576 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs -. CAS latency ( 2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle(2K/32ms) CMOS SDRAM.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
K4S1G0632D SDRAM stacked 1Gb D-die Samsung Electronics
K4S1G0732D SDRAM stacked 1Gb D-die Samsung Electronics
K4S280832B 128M-bit SDRAM Samsung Electronics
K4S281632K 128Mb K-die SDRAM Samsung
K4S510432D 512Mb D-die SDRAM Samsung

Other Datasheets by Samsung Semiconductor

Part Number Description
K4S161622D 512K x 16Bit x 2 Banks Synchronous DRAM
K4S161622E 1M x 16 SDRAM
K4S161622H 16Mb H-die SDRAM Specification
K4S1G0732B-TC75 SDRAM stacked 1Gb B-die
K4S280432A 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
K4S160822D CMOS SDRAM 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL Revision 1.0 October 1999 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.0 (Oct. 1999) K4S160822D Revision History Revision 1.0 (October 1999) CMOS SDRAM -2- Rev. 1.0 (Oct. 1999) K4S160822D 1M x 8Bit x 2 Banks Synchronous DRAM FEATURES • • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs -. CAS latency ( 2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 15.