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K4S161622E - 1M x 16 SDRAM

Download the K4S161622E datasheet PDF. This datasheet also covers the K4S variant, as both devices belong to the same 1m x 16 sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

The K4S161622E is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs -. CAS Latency ( 2 & 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle (2K/32ms) CMOS SDRAM.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K4S-1616.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Samsung Semiconductor

Part Number Description
K4S161622D 512K x 16Bit x 2 Banks Synchronous DRAM
K4S161622H 16Mb H-die SDRAM Specification
K4S160822D 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL
K4S1G0732B-TC75 SDRAM stacked 1Gb B-die
K4S280432A 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
K4S161622E CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Revision 1.1 Jan 2003 Samsung Electronics reserves the right to change products or specification without notice. Rev 1.1 Jan '03 K4S161622E 512K x 16Bit x 2 Banks Synchronous DRAM FEATURES • • • • 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs -. CAS Latency ( 2 & 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 15.