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K4S1G0732B-TC75 - SDRAM stacked 1Gb B-die

Download the K4S1G0732B-TC75 datasheet PDF. This datasheet also covers the K4S1G0732B variant, as both devices belong to the same sdram stacked 1gb b-die family and are provided as variant models within a single manufacturer datasheet.

General Description

The K4S1G0732B is 1,073,741,824bits synchronous high data rate Dynamic RAM organized as 4 x 33,554,432 words by 8 bits, fabricated with SAMSUNG's high performance CMOS technology.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (8K Cycle) CMOS SDRA.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K4S1G0732B_Samsungsemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
K4S1G0732D SDRAM stacked 1Gb D-die Samsung Electronics
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K4S281632K 128Mb K-die SDRAM Samsung
K4S510432D 512Mb D-die SDRAM Samsung

Other Datasheets by Samsung Semiconductor

Part Number Description
K4S160822D 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL
K4S161622D 512K x 16Bit x 2 Banks Synchronous DRAM
K4S161622E 1M x 16 SDRAM
K4S161622H 16Mb H-die SDRAM Specification
K4S280432A 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SDRAM stacked 1Gb B-die (x8) CMOS SDRAM stacked 1Gb B-die SDRAM Specification Revision 1.1 February 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.1 February 2004 SDRAM stacked 1Gb B-die (x8) Revision History Revision 1.0 (August, 2003) - First release. Revision 1.1 (February, 2004) -Corrected typo. CMOS SDRAM Rev. 1.1 February 2004 SDRAM stacked 1Gb B-die (x8) 32M x 8Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.