DESCRIPTION
W (4A) : from Read Control Pin to Write Control R (8A) : from Write Control Pin to Read Control BW0(7B),BW1(7A),BW2(5A),BW3(5B) : from Read Control Pin to Byte Wrtie Control 2) Page 7 STATE DIAGRAM from LEAD NOP to READ NOP 1. Amendment 1) Page 8 WRITE TRUTH TABLE(x36) BW2,BW3 values for WRITE ALL BYTEs( K↑ ) and WRITE ALLBYTEs( K↑ ) : from "H" to " L" 2) Page 13 TIMING WAVE FORMS Note 2 supplement 1. 1.8V I/O supply voltage addition 1) Page 2 FEATURES
2) Page 3,4 PIN NAME VDDQ 3) Page 10, OPERATING CONTITIONS 4) Page 11 AC TEST CONTITIONS 2. Amendment 1) Page 15 BOUNDARY SCAN ORDER EXIT 1. Icc, Isb addition 2. 1.8V Vddq addition 1. Reserved pin for high density name change from NC to Vss/SA 1. Release Icc. part # -20 -16 -13 -10 x18 From 500 To 520 From 530 490 460 x36 To 600 550 490 Draft Date April 30, 2001 May, 13, 2001 Remark Advance Advance 0.2 May, 26, 2001 Advance June, 11, 2001 Advance 0.3 0.4 Sep, 03, 2001 Nov, 30, 2001 Advance Preliminary 0.5 0.6 May, 22. 2002 Preliminary 1.0 1.
Samsung semiconductor
