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K9F1G08Q0A - FLASH MEMORY

General Description

Offered in 128Mx8bit the K9F1G08X0A is 1G bit with spare 32M bit capacity.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

Key Features

  • Voltage Supply -1.8V device(K9F1G08Q0A): 1.70V~1.95V -3.3V device(K9F1G08U0A): 2.7 V ~3.6 V.
  • Organization - Memory Cell Array : (128M + 4,096K)bit x 8bit - Data Register : (2K + 64)bit x8bit - Cache Register : (2K + 64)bit x8bit.
  • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte.
  • Page Read Operation - Page Size : 2K-Byte - Random Read : 25µs(Max. ) - Serial Access : 30ns(Min. ) : (K9F1G08U0A) 50ns(Min. ) : (K9F1G08Q0A).

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com K9F1G08Q0A K9F1G08U0A FLASH MEMORY Document Title 128M x 8 Bit NAND Flash Memory Revision History Revision No 0.0 0.1 History 1. Initial issue 1. The tADL(Address to Data Loading Time) is added. - tADL Minimum 100ns (Page 11, 23~26) - tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle at program operation. 2. Added Addressing method for program operation Draft Date Aug. 24. 2003 Jan. 27. 2004 Remark Advance Preliminary 0.2 0.3 1. Add the Protrusion/Burr value in WSOP1 PKG Diagram. 1. PKG(TSOP1, WSOP1) Dimension Change Apr. 23. 2004 May. 19. 2004 Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD.