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K9F1G08R0A - 128M x 8 Bit / 256M x 8 Bit NAND Flash Memory

General Description

of Copy-back program is changed 4.

Voltage range is changed -1.7V~1.95V -> 1.65V~1.95V 5.

Note2 of Command Sets is added 1.

Key Features

  • Voltage Supply -1.8V device(K9F1G08R0A): 1.65V~1.95V -3.3V device(K9F1G08U0A): 2.7 V ~3.6 V.
  • Organization - Memory Cell Array : (128M + 4,096K)bit x 8bit - Data Register : (2K + 64)bit x8bit - Cache Register : (2K + 64)bit x8bit.
  • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte.
  • Page Read Operation - Page Size : 2K-Byte - Random Read : 25µs(Max. ) - Serial Access : 30ns(Min. ) - 3.3v device 50ns(Min. ) -1.8v device.

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Other Datasheets by Samsung Semiconductor

Part Number Description
K9F1G08D0M 128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
K9F1G08Q0A FLASH MEMORY
K9F1G08Q0M 128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
K9F1G08U0A FLASH MEMORY
K9F1G08U0A 128M x 8 Bit / 256M x 8 Bit NAND Flash Memory

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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K9F1G08R0A K9F1G08U0A K9K2G08U1A FLASH MEMORY Document Title 128M x 8 Bit / 256M x 8 Bit NAND Flash Memory Revision History Revision No 0.0 0.1 History 1. Initial issue 1. The tADL(Address to Data Loading Time) is added. - tADL Minimum 100ns (Page 11, 23~26) - tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle at program operation. 2. Added Addressing method for program operation Draft Date Aug. 24. 2003 Jan. 27. 2004 Remark Advance Preliminary www.DataSheet4U.com 0.2 0.3 0.4 1. Add the Protrusion/Burr value in WSOP1 PKG Diagram. 1. PKG(TSOP1, WSOP1) Dimension Change 1. Technical note is changed 2. Notes of AC timing characteristics are added 3. The description of Copy-back program is changed 4. Voltage range is changed -1.