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KM416S8030B - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

Download the KM416S8030B datasheet PDF. This datasheet also covers the KM4-16S variant, as both devices belong to the same 128mbit sdram 2m x 16bit x 4 banks synchronous dram lvttl family and are provided as variant models within a single manufacturer datasheet.

General Description

The KM416S8030B is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (KM4-16S-8030B.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
KM416S1020BT-G10T CMOS 16M-Bit SDRAM ETC
KM416S1120AT 521K x 16-Bit x 2 Bank SDRAM Samsung Electronics
KM416S1120D 512K x 16bit x 2 Banks Synchronous DRAM LVTTL ETC
KM416S4020A CMOS SDRAM Samsung Electronics
KM416S4020B CMOS SDRAM Samsung Electronics

Other Datasheets by Samsung Semiconductor

Part Number Description
KM416S8030BN 128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
KM416S8030 2M x 16Bit x 4 Banks Synchronous DRAM
KM416S1020C 1M x 16 SDRAM
KM416S1021C 512K x 16-Bit x 2-Bank SDRAM
KM416S4030C 1M x 16Bit x 4 Banks Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
KM416S8030B CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 1999 KM416S8030B Revision History Revision 0.0 (May 15, 1999) CMOS SDRAM • Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER. • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER. • Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.