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KM416S8030BN - 128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

General Description

The KM416S8030B is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle).

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Other Datasheets by Samsung Semiconductor

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KM416S8030B 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
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Full PDF Text Transcription (Reference)

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shrink-TSOP KM416S8030BN Preliminary CMOS SDRAM 128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL www.DataSheet4U.com Revision 0.1 Aug. 1999 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Aug. 1999 shrink-TSOP KM416S8030BN Revision History Version 0.0 (July 2, 1999, Preliminary) • Preliminary specification for shrink-TSOP. Preliminary CMOS SDRAM Version 0.1 (August 24, 1999, Preliminary) • Added Note 5 in OPERATING AC PARAMETER. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported. • SAMSUNG recommends tRDL=2CLK and tDAL=2CLK+20ns. Rev. 0.1 Aug. 1999 shrink-TSOP KM416S8030BN Preliminary CMOS SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM in New Shrink-TSOP(sTSOP) FEATURES • JEDEC standard 3.