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ST2309ES Datasheet PDF

Stanson Technology ST2309ES

ST2309ES is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management, other battery powered circuits, and low in-line power loss are required.
Part No. ST2309ES
Datasheet ST2309ES Download
Manufacturer
Stanson Technology
Description P-Channel Enhancement Mode MOSFET
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ST2309ES datasheet page 1 preview

DESCRIPTION

The product is in a very small outline surface mount package. PIN CONFIGURATION SOT-23 3 D G S 1 2 FEATURE ! -60V/-3.0A, RDS(ON) = 160m-ohm @VGS = -10V ! -60V/-1.5A, RDS(ON) = 200m-ohm @VGS = -4.5V ! Super high density cell design for extremely low RDS(ON) ! Exceptional on-resistance and maximum DC current capability ! SOT-23 package design 1.Gate 2.Source 3.Drain PART MARKING SOT-23 3 21YA 1 2 Y: Year Code A: Process Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA ST2309ES 2015. Rev.1 ST2309ES P Channel Enhancement Mode MOSFET -3.0A ABSOULTE

MAXIMUM RATINGS

(Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage VDSS -60 Gate-Source Voltage Continuous Drain CurrentTJ=150℃) TA=25℃ TA=70℃ Pulsed Drain Current VGSS ID IDM ±20 -3.0 -1.3 -9 Continuous Source Current (Diode Conduction) IS Power Dissipation TA=25℃ TA=70℃ PD Operation Junction Temperature TJ -2.2 1.5 0.8 150 Storgae Temperature Range TSTG -55/150 Thermal Resistance-Junction to Ambient RθJA 100 Unit V V A A A W ℃ ℃ ℃/W STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA ST2309ES 2015.
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