ST2309ES Datasheet | Stanson Technology

DESCRIPTION ST2309ES is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management, other battery powered circuits, and low in-line power loss are required. The product is in a very small outline surface mount package. PIN CONFIGURATION SOT-23 3 D FEATURE ! -60V/-3.0A, RDS(ON) = 160m-ohm @VGS = -10V ! -60V/-1.5A, RDS(ON) = 200m-ohm @VGS = -4.5V ! Super high density cell design for extremely low RDS(ON) ! Exceptional on-resistance and maximum DC current capability ! SOT-23 package design 1.Gate 2.Source 3.Drain PART MARKING SOT-23 21YA Y: Year Code A: Process Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA .stansontech. ST2309ES 2015. Rev.1 P Channel Enhancement Mode MOSFET -3.0A ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage VDSS -60 Gate-Source Voltage Continuous Drain Current TJ=150℃) TA=25℃ TA=70℃ Pulsed Drain Current VGSS ID IDM ±20 -3.0 -1.3 -9 Continuous Source Current (Diode Conduction) Power...