The following content is an automatically extracted verbatim text
from the original manufacturer datasheet and is provided for reference purposes only.
View original datasheet text
ST2317S23RG
P Channel Enhancement Mode MOSFET
-5.0A
DESCRIPTION
ST2317S23RG is the P-Channel logic enhancement mode power field effect transistor is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching and low in-line power loss are required in a very small outline surface mount package.
PIN CONFIGURATION SOT-23-3L
3
D
G
S
1
2
1.Gate 2.Source 3.Drain
PART MARKING SOT-23-3L
3
17YW
1
2
Y: Year Code W: Week Code
FEATURE
l -40V/-5.0A, RDS(ON) = 37mΩ (Typ.) @VGS = -10V
l -40V/-3.0A, RDS(ON) = 51mΩ @VGS = -4.