ST2318SRG Datasheet | Stanson Technology

DESCRIPTION ST2318SRG is the N-Channel logic enhancement mode power field effect transistor is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management, other battery powered circuits, and low in-line power loss are needed in a very small outline surface mount package. PIN CONFIGURATION SOT-23 1.Gate 2.Source 3.Drain PART MARKING SOT-23 18YW Y: Year Code W: Week Code FEATURE 40V/3.9A, RDS(ON) = 42mΩ (Typ.) @VGS = 10V 40V/3.5A, RDS(ON) = 53mΩ @VGS = 4.5V 40V/2.0A, RDS(ON) = 75 mΩ @VGS = 2.5V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability SOT-23 package design STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA .stansontech. ST2318SRG 2009. V1 N Channel Enhancement Mode MOSFET 3.9A ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage VDSS Gate-Source Voltage VGSS ±20 Continuous Drain Current TJ=150℃) TA=25℃ TA=70℃ 3.9 3.0 Pulsed Drain Current Continuous Source Current (Diode Conduction) Power...