ST2319SRG Datasheet | Stanson Technology

DESCRIPTION ST2319SRG is the P-Channel logic enhancement mode power field effect transistor is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management and other battery powered circuits where high-side switching and low in-line power loss are required in a very small outline surface mount package. PIN CONFIGURATION SOT-23 3 D 1.Gate 2.Source 3.Drain PART MARKING SOT-23 19YW Y: Year Code W: Week Code FEATURE -40V/-3.5A, RDS(ON) = 75mΩ (Typ.) @VGS = -10V -40V/-2.8A, RDS(ON) = 105mΩ @VGS = -4.5V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability SOT-23 package design STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA .stansontech. ST2319SRG 2009. Rev.1 P Channel Enhancement Mode MOSFET -3.5A ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage VDSS -40 Gate-Source Voltage Continuous Drain Current TJ=150℃) TA=25℃ TA=70℃ Pulsed Drain Current VGSS ID IDM ±20 -3.5 -2.8 -20 Continuous Source Current (Diode Conduction) -1.2 Power Dissipation TA=25℃...