STN1810 Datasheet PDF | Stanson Technology

Stanson Technology STN1810

STN1810 is the N-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These applications such as notebook computer power management and other battery powered circuits where high-side switching, low inline power loss and resistance to transients are melded.

Part No.	STN1810
Datasheet	STN1810 Download
Manufacturer	Stanson Technology
Description	MOSFET
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DESCRIPTION

PIN CONFIGURATION SOP-8 FEATURE 60V/8.0A, RDS(ON) = 140mΩ (Typ.) @VGS = 10V 60V/6.5.0A, RDS(ON) = 150mΩ @VGS = 7.0V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability SOP-8 package design PART MARKING Y: Year Code A: Process Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA Copyright © 2007, Stanson Corp. STN1810 2009. V1 STN1810 N Channel Enhancement Mode MOSFET 8.0A ABSOULTE

MAXIMUM RATINGS

(Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage VDSS 100 Gate-Source Voltage Continuous Drain Current (TJ=150℃) Pulsed Drain Current TA=25℃ TA=70℃ VGSS ID IDM ±20 8.0 6.0 12 Continuous Source Current (Diode Conduction) Power Dissipation TA=25℃ TA=70℃ Operation Junction Temperature IS PD TJ 2.3 2.8 1.8 150 Storgae Temperature Range TSTG -55/150 Thermal Resistance-Junction to Ambient RθJA 80 Unit V V A A A W ℃ ℃ ℃/W STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA Copyright © 2007, Stanson Corp.