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TC58NVG6D2GTA00 - 64 GBIT (8G X 8 BIT) CMOS NAND E2PROM

General Description

The TC58NVG6D2 is a single 3.3 V 64 Gbit (74,594,648,064 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 640) bytes  256 pages  4124 blocks.

Key Features

  • Organization Memory cell array Register Page size Block size.
  • TC58NVG6D2G 8832  512K  8 8832  8 8832 bytes (2M  160 K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 3996 blocks Max 4124 blocks Power supply VCC  2.7 V to 3.6 V Access time Cell array to register Serial Read Cycle Program/Erase ti.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TOSHIBA CONFIDENTIAL TENTATIVE TC58NVG6D2GTA00 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 64 GBIT (8G  8 BIT) CMOS NAND E PROM (Multi-Level-Cell) DESCRIPTION The TC58NVG6D2 is a single 3.3 V 64 Gbit (74,594,648,064 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 640) bytes  256 pages  4124 blocks. The device has two 8832-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 8832-byte increments. The Erase operation is implemented in a single block unit (2 Mbytes  160 Kbytes: 8832 bytes  256 pages). The TC58NVG6D2 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.