WEDPN4M64V Datasheet PDF - White Electronic Designs 4M x 64 SDRAM Specs

WEDPN4M64V - 4M x 64 SDRAM

Datasheet Summary

Description

The 32MByte (256Mb) SDRAM is a high-speed CMOS, dynamic random-access ,memory using 4 chips containing 67,108,864 bits.

Each chip is internally conﬁgured as a quad-bank DRAM with a synchronous interface.

Each of the chip’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.

Features

High Frequency = 100, 125, 133MHz Package:.
219 Plastic Ball Grid Array (PBGA), 21 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 4096 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 4M x 64.
User Conﬁgu.

Datasheet Details

Part number	WEDPN4M64V
Manufacturer	White Electronic Designs
File Size	344.73 KB
Description	4M x 64 SDRAM
Datasheet	WEDPN4M64V Datasheet
Additional preview pages of the WEDPN4M64V datasheet.

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Full PDF Text Transcription

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White Electronic Designs 4Mx64 Synchronous DRAM FEATURES High Frequency = 100, 125, 133MHz Package: • 219 Plastic Ball Grid Array (PBGA), 21 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 4096 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 4M x 64 • User Conﬁgurable as 2x4Mx32 or 4x4Mx16 Weight: WEDPN4M64V-XBX - 2 grams typical WEDPN4M64V-XBX GENERAL DESCRIPTION The 32MByte (256Mb) SDRAM is a high-speed CMOS, dynamic random-access ,memory using 4 chips containing 67,108,864 bits.

Published: Dec 15, 2005 |