WEDPN4M72V Datasheet PDF - White Electronic Designs 4M x 72 SDRAM Specs

WEDPN4M72V - 4M x 72 SDRAM

Datasheet Summary

Description

The 32MByte (256Mb) SDRAM is a high-speed CMOS, dynamic random-access ,memory using 5 chips containing 67,108,864 bits.

Each chip is internally conﬁgured as a quad-bank DRAM with a synchronous interface.

Each of the chip’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.

Features

S.
Package:.
219 Plastic Ball Grid Array (PBGA), 25 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 4096 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as.

Datasheet Details

Part number	WEDPN4M72V
Manufacturer	White Electronic Designs
File Size	489.50 KB
Description	4M x 72 SDRAM
Datasheet	WEDPN4M72V Datasheet
Additional preview pages of the WEDPN4M72V datasheet.

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Full PDF Text Transcription

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White Electronic Designs 4Mx72 Synchronous DRAM* FEATURES            Package:  219 Plastic Ball Grid Array (PBGA), 25 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 4096 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 4M x 72 Weight: WEDPN4M72V-XBX - 2 grams typical High Frequency = 100, 125MHz WEDPN4M72V-XBX GENERAL DESCRIPTION The 32MByte (256Mb) SDRAM is a high-speed CMOS, dynamic random-access ,memory using 5 chips containing 67,108,864 bits.

Published: Dec 15, 2005 |