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DS90CR482 - 48-Bit LVDS

This page provides the datasheet information for the DS90CR482, a member of the DS90CR481 48-Bit LVDS family.

Description

The DS90CR481 transmitter converts 48 bits of CMOS/TTL data into eight LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a ninth LVDS link.

Features

  • 1.
  • 2 3.168 Gbits/sec Bandwidth with 66 MHz Clock.
  • 5.376 Gbits/sec Bandwidth with 112 MHz Clock.
  • 65 - 112 MHz Input Clock Support.
  • LVDS SER/DES Reduces Cable and Connector Size.
  • Pre-Emphasis Reduces Cable Loading Effects.
  • Optional DC Balance Encoding Reduces ISI Distortion.
  • Cable Deskew of +/.
  • 1 LVDS Data Bit Time (up to 80 MHz Clock Rate).
  • 5V Tolerant TxIN and Control Input Pins.
  • Flow Through Pinout for Easy P.

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Datasheet preview – DS90CR482

Datasheet Details

Part number DS90CR482
Manufacturer Texas Instruments
File Size 1.64 MB
Description 48-Bit LVDS
Datasheet download datasheet DS90CR482 Datasheet
Additional preview pages of the DS90CR482 datasheet.

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Full PDF Text Transcription

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DS90CR481, DS90CR482 www.ti.com SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013 DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz Check for Samples: DS90CR481, DS90CR482 FEATURES 1 •2 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • Cable Deskew of +/−1 LVDS Data Bit Time (up to 80 MHz Clock Rate) • 5V Tolerant TxIN and Control Input Pins • Flow Through Pinout for Easy PCB Design • +3.
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