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LP2995 - DDR Termination Regulator

General Description

The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM.

The device contains a high-speed operational amplifier to provide excellent response to load transients.

Key Features

  • 1.
  • 2 Low Output Voltage Offset.
  • Works with +5v, +3.3v and 2.5v Rails.
  • Source and Sink Current.
  • Low External Component Count.
  • No External Resistors Required.
  • Linear Topology.
  • Available in SOIC-8, SO PowerPAD-8 or WQFN-16 Packages.
  • Low Cost and Easy to Use.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES 1 •2 Low Output Voltage Offset • Works with +5v, +3.3v and 2.5v Rails • Source and Sink Current • Low External Component Count • No External Resistors Required • Linear Topology • Available in SOIC-8, SO PowerPAD-8 or WQFN-16 Packages • Low Cost and Easy to Use APPLICATIONS • DDR Termination Voltage • SSTL-2 • SSTL-3 DESCRIPTION The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.