5V-to-3.3V Datasheet | Specifications & PDF Download

OM9551SP, OM9552SP, OM9553SP, OM9554SP 5V Input, 3A Output Current +3.3V, +2.5V +1.8V, +1.5V Output Switching Regulator Three Terminal Package FEATU

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OM9551SP, OM9552SP, OM9553SP, OM9554SP 5V Input, 3A Output Current +3.3V, +2.5V +1.8V, +1.5V Output Switching Regulator Three Terminal Package FEATU

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Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurab

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OM9551SP, OM9552SP, OM9553SP, OM9554SP 5V Input, 3A Output Current +3.3V, +2.5V +1.8V, +1.5V Output Switching Regulator Three Terminal Package FEATU

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NB7L11M 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination Description http://onsemi.com MARKI

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DATA SHEET www.onsemi.com 2.5 V / 3.3 V 7 GHz / 10 Gbps Differential 1:4 LVPECL Fanout Buffer Multi−Level Inputs with Internal Termination NB7L14 Des

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Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurab

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Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurab

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NB3L8543S 2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs with Clock Enable and Clock Select Description The NB3L8543S is a hi

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NB3L8533 2.5V/3.3V Differential 2:1 MUX to 4 LVPECL Fanout Buffer Description The NB3L8533 is a low skew 1:4 LVPECL Clock fanout buffer designed expl

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Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurab

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NB3L8504S 2.5 V / 3.3 V 1:4 Differential Input to LVDS Fanout Buffer / Translator Description The NB3L8504S is a differential 1:4 LVDS fanout buffer/

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LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP FEATURES n Smallest Pin-Compatible Octal DACs: LTC2600: 16 Bits LTC26

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NB3L83948C 2.5 V / 3.3 V Differential and LVTTL/LVCMOS 2:1 MUX to 1:12 LVCMOS Fanout Description The NB3L83948C is a pure 2.5 V / 3.3 V (VDD = VDDO)

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NB3V110xC Series 3.3V/2.5V/1.8V LVCMOS Low Skew Fanout Buffer Family Description The NB3V110xC are a modular, high−performance, low−skew, general pu

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Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurab

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Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurab

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INTEGRATED CIRCUITS 74ALVT162245 2.5V/3.3V ALVT 16-bit transceiver with 30W termination resistors (3-State) Product specification Supersedes data of

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NB3L853141 2.5V/3.3V 1:5 LVPECL Fanout Buffer Description The NB3L853141 is a low skew 1:5 LVPECL Clock fanout buffer designed explicitly for low out

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NB3H5150-01 2.5V / 3.3V Low Noise Multi-Rate Clock Generator Description The NB3H5150−01 is a high performance Multi−Rate Clock generator which si

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