74368 Hex buffer/line driver; 3state; inve.
74368 - Hex buffer/line driver
74368 Hex buffer/line driver; 3state; inverting PDF datasheet OE1 1 • 1A 2 1Y 3 2A 4 2Y 5 3A 6 3Y 7 GND 8 Pin 16 Vcc 1 15 OE2 2 14 6A 3.M5M5V5636GP16 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
2001.July Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5V.M5M5Y5636TG-22 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
2001.June Rev.0.0 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5.M5M5Y5672TG-22 - 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5Y5.M5M5Y5672TG-25 - 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5Y5.SN74368A - Hex Bus Driver
PACKAGE OPTION ADDENDUM www.ti.com PACKAGING INFORMATION Orderable Device JM38510/32201B2A Status Package Type Package Pins Package Eco Plan (1) .M5M5T5636GP-20 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
January 31, 2003 Rev.0.6 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. DESCRIPTION The M5M5T5636G.M5M5T5636UG-20 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
January 14, 2003 Rev.0.7 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. DESCRIPTION The M5M5T5636U.M5M5T5636UG-22 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
January 14, 2003 Rev.0.7 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. DESCRIPTION The M5M5T5636U.M5M5T5636UG-25 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
January 14, 2003 Rev.0.7 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. DESCRIPTION The M5M5T5636U.M5M5Y5636TG-20 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
2001.June Rev.0.0 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5.M5M5Y5636TG-25 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
2001.June Rev.0.0 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5.M5M5Y5672TG-20 - 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5Y5.M5M5T5636GP-25 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
January 31, 2003 Rev.0.6 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. DESCRIPTION The M5M5T5636G.M5M5T5636GP-22 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
January 31, 2003 Rev.0.6 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. DESCRIPTION The M5M5T5636G.M5M5T5672TG-20 - 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
Preliminary Notice: This is not final specification. Some parametric limits are subject to change. DESCRIPTION The M5M5T5672TG is a family of 18M bit .M5M5V5636UG-16 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DESCRIPTION The M5M5V5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles .