74ACT10 Datasheet | Specifications & PDF Download

MC74AC10, MC74ACT10 Triple 3-Input NAND Gate High−Performance Silicon−Gate CMOS Features • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inpu

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MC74AC109, MC74ACT109 Dual JK Positive Edge−Triggered Flip−Flop The MC74AC109/74ACT109 consists of two high−speed completely independent transition

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www.DataSheet4U.com MC74AC10 MC74ACT10 Triple 3ĆInput NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs TRIPLE 3-INPUT NAND G

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• Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems • Reduces Undershoot and Overshoot Caused By Line Reflections • Repe

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HD74AC107/HD74ACT107 Dual JK Flip-Flop (with Separate Clear and Clock) REJ03D0243–0200Z (Previous ADE-205-363 (Z)) Rev.2.00 Jul.16.2004 Description T

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TECHNICAL DATA IN74ACT109 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT109 is identical in pinout to the LS/ALS109,

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TECHNICAL DATA www.DataSheet4U.com KK74ACT10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The KK74ACT10 is identical in pinout to the LS/A

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CD74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Co

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D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V SN54ACT10 . . . J OR W PACKAGE SN74ACT10 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW

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HD74AC107/HD74ACT107 Dual JK Flip-Flop (with Separate Clear and Clock) Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a se

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TECHNICAL DATA IN74ACT10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The IN74ACT10 is identical in pinout to the LS/ALS10, HC/HCT10. The I

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54AC 74AC10  74ACT10 Triple 3-Input NAND Gate March 1993 54AC 74AC10  74ACT10 Triple 3-Input NAND Gate General Description The ’AC ’ACT10 contains

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TECHNICAL DATA www.DataSheet4U.com KK74ACT109 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74ACT109 is identical in pin

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74AC08 • 74ACT08 Quad 2-Input AND Gate November 1988 Revised November 1999 74AC08 • 74ACT08 Quad 2-Input AND Gate General Description The AC/ACT08 c

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CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS327 – JANUARY 2003 D Inputs Are TTL-Voltage Compatible D

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• Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems • Reduces Undershoot and Overshoot Caused By Line Reflections • Repe

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SN74ACT10-Q1 TRIPLE 3-INPUT POSITIVE-NAND GATE D Qualified for Automotive Applications D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5

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D Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D R

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