www.DataSheet4U.com CT ULTRA SMALL AUTOMOTIVE REL.
74ACT11245 - OCTAL BUS TRANSCEIVER
D 3-State Outputs Drive Bus Lines Directly D Inputs Are TTL-Voltage Compatible D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and G.ACT112 - ULTRA SMALL AUTOMOTIVE RELAY
www.DataSheet4U.com CT ULTRA SMALL AUTOMOTIVE RELAY CT-RELAYS • Simple footprint enables ease of PC board layout 10 terminals layout 17.4 .685 14 .HD74ACT112 - Dual JK Negative Edge-Triggered Flip-Flop
HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous .HD74ACT112 - Dual JK Negative Edge-Triggered Flip-Flop
HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop REJ03D0244–0200Z (Previous ADE-205-364 (Z)) Rev.2.00 Jul.16.2004 Description The HD74A.IN74ACT112 - Dual J-K Negative-Edge-Triggered Flip-Flop
TECHNICAL DATA IN74ACT112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT112 is identical in pinout to the LS/ALS112,.54ACT112 - Dual JK Negative Edge-Triggered Flip-Flop
www.DataSheet4U.com 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop September 1998 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop General De.KK74ACT112 - Set and Reset High-Speed Silicon-Gate CMOS
TECHNICAL DATA www.DataSheet4U.com KK74ACT112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74ACT112 is identical in pin.74ACT11238 - 3-Line to 8-Line Decoder/DeMultiplexer
ą • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems • Noninverting Version of ′ACT11138 • Incorporates 3 Enable Inp.54ACT11241 - OCTAL BUFFERS/LINE DRIVERS
• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Lay.74ACT11241 - OCTAL BUFFERS/LINE DRIVERS
• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Lay.74ACT11258 - Quadruple 2-Line To 1-Line Data Selector/Multiplexer
ą 74ACT11258 QUADRUPLE 2ĆLINE TO 1ĆLINE DATA SELECTOR/MULTIPLEXER WITH 3ĆSTATE OUTPUTS SCAS056A − D3278, JANUARY 1989 − REVISED APRIL 1993 • Inputs A.74ACT11273 - OCTAL D-TYPE FLIP-FLOP
• Inputs Are TTL-Voltage Compatible • Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators • Flow-Through Architecture Op.54ACT11280 - 9-BIT PARITY GENERATORS/CHECKERS
• Inputs Are TTL-Voltage Compatible • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity • Flow-Through Architectu.74ACT11280 - 9-BIT PARITY GENERATORS/CHECKERS
• Inputs Are TTL-Voltage Compatible • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity • Flow-Through Architectu.TC74ACT112F - Dual J-K Flip-Flop
TC74ACT112P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT112P, TC74ACT112F Dual J-K Flip Flop with Preset and Clear The TC74AC.TC74ACT112P - Dual J-K Flip-Flop
TC74ACT112P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT112P, TC74ACT112F Dual J-K Flip Flop with Preset and Clear The TC74AC.74ACT11286 - 9-Bit Parity Generator/Checker
D Inputs Are TTL-Voltage Compatible D Generates Either Odd or Even Parity for Nine Data Lines D Cascadable for n-Bits Parity D Center-Pin VCC and GND .74ACT11257 - QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER
74ACT11257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS SCAS053B − JANUARY 1989 − REVISED APRIL 1996 D Inputs Are TTL-Vo.74ACT11253 - DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS
54ACT11253, 74ACT11253 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCAS040A – D3110, MARCH 1988 – REVISED APRIL 1993 • Inputs Are TT.74ACT11244 - OCTAL BUFFER/LINE DRIVER
D 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers D Inputs Are TTL-Voltage Compatible D Flow-Through Architecture Optimizes PCB Lay.