The AS7C3364NTD36B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 65,536 words × 32 or 36 bits and incorporates a LATE LATE Write.
Features
Organization: 65,536 words × 32 or 36 bits.
NTD™ architecture for efficient bus operation.
Fast clock speeds to 200 MHz.
Fast clock to data access: 3.0/3.5/4.0 ns.
Fast OE access time: 3.0/3.5/4.0 ns.
Fully synchronous operation.
Asynchronous output enable control.
Available in 100-pin TQFP package www. DataSheet4U. com.
April 2005
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AS7C3364NTD32B AS7C3364NTD36B
3.3V 64K×32/36 Pipelined SRAM with NTDTM
Features
• Organization: 65,536 words × 32 or 36 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.
AS7C3364NTD32B Datasheet
