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Cypress Semiconductor Electronic Components Datasheet

CY2305 Datasheet

Low Cost 3.3 V Zero Delay Buffer

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CY2305
CY2309
Low Cost 3.3 V Zero Delay Buffer
Low Cost 3.3 V Zero Delay Buffer
Features
10 MHz to 100/133 MHz operating range, compatible with CPU
and PCI bus frequencies
Zero input-output propagation delay
60-ps typical cycle-to-cycle jitter (high drive)
Multiple low skew outputs
85 ps typical output-to-output skew
One input drives five outputs (CY2305)
One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)
Compatible with Pentium-based systems
Test Mode to bypass phase-locked loop (PLL) (CY2309)
Packages:
8-pin, 150-mil SOIC package (CY2305)
16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)
3.3 V operation
Commercial and industrial temperature ranges
Functional Description
The CY2309 is a low-cost 3.3 V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305 is an 8-pin version of the
CY2309. It accepts one reference input, and drives out five low
skew clocks. The -1H versions of each device operate at up to
100-/133 MHz frequencies, and have higher drive than the -1
devices. All parts have on-chip PLLs which lock to an input clock
on the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
The CY2309 has two banks of four outputs each, which can be
controlled by the select inputs as shown in Select Input Decoding
on page 5. If all output clocks are not required, BankB can be
three-stated. The select inputs also allow the input clock to be
directly applied to the outputs for chip and system testing
purposes.
The CY2305 and CY2309 PLLs enter a power-down mode when
there are no rising edges on the REF input. In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25.0 A current draw for these parts. The CY2309 PLL
shuts down in one additional case as shown in Select Input
Decoding on page 5.
Multiple CY2305 and CY2309 devices can accept the same input
clock and distribute it. In this case, the skew between the outputs
of two devices is guaranteed to be less than 700 ps.
The CY2305/CY2309 is available in two or three different
configurations, as shown in Ordering Information on page 16.
The CY2305-1/CY2309-1 is the base part. The CY2305-1H/
CY2309-1H is the high-drive version of the -1, and its rise and
fall times are much faster than the -1.
For a complete list of related documentation, click here.
Logic Block Diagram
REF
S2
S1
PLL MUX
Select Input
Decoding
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07140 Rev. *X
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 27, 2017


Cypress Semiconductor Electronic Components Datasheet

CY2305 Datasheet

Low Cost 3.3 V Zero Delay Buffer

No Preview Available !

CY2305
CY2309
Contents
Pin Diagram ....................................................................... 3
Pin Description ................................................................. 3
Pin Diagram ....................................................................... 4
Pin Description ................................................................. 4
Select Input Decoding ...................................................... 5
Zero Delay and Skew Control .......................................... 5
Absolute Maximum Conditions ....................................... 6
Operating Conditions ....................................................... 6
Electrical Characteristics ................................................. 6
Operating Conditions ....................................................... 7
Electrical Characteristics ................................................. 7
Test Circuits ...................................................................... 8
Thermal Resistance .......................................................... 8
Typical Duty Cycle and IDD Trends ................................. 9
Typical Duty Cycle and IDD Trends ............................... 10
Switching Characteristics .............................................. 11
Switching Characteristics .............................................. 12
Switching Characteristics .............................................. 13
Switching Characteristics .............................................. 14
Switching Waveforms .................................................... 15
Ordering Information ...................................................... 16
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 17
Package Drawing and Dimensions ............................... 18
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Errata ............................................................................... 21
Part Numbers Affected .............................................. 21
CY2305/CY2309 Errata Summary ............................ 22
CY2305/CY2309 Qualification Status ....................... 22
Document History Page ................................................. 23
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC®Solutions ....................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Document Number: 38-07140 Rev. *X
Page 2 of 25


Part Number CY2305
Description Low Cost 3.3 V Zero Delay Buffer
Maker Cypress
Total Page 25 Pages
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