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Cypress Semiconductor Electronic Components Datasheet

CY2309C Datasheet

Zero Delay Buffers

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CY2305C
CY2309C
3.3 V Zero Delay Clock Buffer
3.3 V Zero Delay Clock Buffer
Features
10 MHz to 100–133 MHz operating range
Zero input and output propagation delay
Multiple low skew outputs
One input drives five outputs (CY2305C)
One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)
50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
Test mode to bypass phase locked loop (PLL) (CY2309C) only,
see Select Input Decoding on page 6
Available in space saving 16-pin 150 Mil small outline
integrated circuit (SOIC) or 4.4 mm thin shrunk small outline
package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil
SOIC package (CY2305C)
3.3 V operation
Commercial, industrial and automotive-A flows available
Functional Description
The CY2305C and CY2309C are die replacement parts for
CY2305 and CY2309.
The CY2309C is a low-cost 3.3 V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305C is an 8-pin version of the
CY2309C. It accepts one reference input and drives out five low
skew clocks. The -1H versions of each device operate up to
100 MHz–133 MHz frequencies and have higher drive than the
-1 devices. All parts have on-chip phase locked loops (PLLs)
which lock to an input clock on the REF pin. The PLL feedback
is on-chip and is obtained from the CLKOUT pad.
The CY2309C has two banks of four outputs each that are
controlled by the select inputs as shown in the Select Input
Decoding on page 6. If all output clocks are not required, Bank
B is three-stated. The input clock is directly applied to the outputs
by the select inputs for chip and system testing purposes.
The CY2305C and CY2309C PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off. This
results in less than 12.0 A of current draw for commercial
temperature devices and 25.0 A for industrial and automotive-A
temperature parts. The CY2309C PLL shuts down in one
additional case as shown in the Select Input Decoding on page 6.
In the special case when S2:S1 is 1:0, the PLL is bypassed and
REF is output from DC to the maximum allowable frequency. The
part behaves as a non-zero delay buffer in this mode and the
outputs are not three-stated.
The CY2305C or CY2309C is available in two or three different
configurations as shown in the Ordering Information on page 15.
The CY2305C-1 or CY2309C-1 is the base part. The CY2305-1H
or CY2309-1H is the high drive version of the -1. Its rise and fall
times are much faster than the -1.
For a complete list of related documentation, click here.
Logic Block Diagram – CY2305C
REF
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07672 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 27, 2017


Cypress Semiconductor Electronic Components Datasheet

CY2309C Datasheet

Zero Delay Buffers

No Preview Available !

Logic Block Diagram – CY2309C
PLL
REF
MUX
S2
Select Input
Decoding
S1
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CY2305C
CY2309C
Document Number: 38-07672 Rev. *Q
Page 2 of 22


Part Number CY2309C
Description Zero Delay Buffers
Maker Cypress Semiconductor
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CY2309C Datasheet PDF





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