CY7C1041BV33
Features
- High speed
- t AA = 12 ns
- Low active power
- 612 m W (max.)
- Low CMOS standby power (mercial L version)
- 1.8 m W (max.)
- 2.0V Data Retention (600 µW at 2.0V retention)
- Automatic power-down when deselected
- TTL-patible inputs and outputs
- Easy memory expansion with CE and OE features written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is acplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a plete description of read and write modes. The input/output pins...
