CY7C1319KV18 Datasheet 18-Mbit DDR II SRAM Four-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Datasheet Details

Part number	CY7C1319KV18
Manufacturer	Cypress (now Infineon)
File Size	816.04 KB
Description	18-Mbit DDR II SRAM Four-Word Burst Architecture
Download	CY7C1319KV18 Download (PDF)

CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II architecture.

The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter.

Addresses for read and write are latched on alternate rising edges of the input (K) clock.

CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst.

18-Mbit density (1M × 18, 512K × 36).
333-MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high speed systems.
Synchronous.

Part Number	Description
CY7C1319BV18	1.8V Synchronous Pipelined SRAM
CY7C131	1K x 8 Dual-Port Static RAM
CY7C1310BV18	1.8V Synchronous Pipelined SRAM
CY7C1311AV18	(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311BV18	(CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311CV18	(CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311JV18	(CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1311KV18	18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1312BV18	1.8V Synchronous Pipelined SRAM
CY7C1312KV18	18-Mbit QDR II SRAM Two-Word Burst Architecture