CY7C1310BV18 Datasheet - Cypress Semiconductor

CY7C1310BV18 1.8V Synchronous Pipelined SRAM

CY7C1310BV18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 250 MHz clock for high bandwidth

* 2-word burst on all accesses

* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz

* Two input clocks

Datasheet Details

CY7C1310BV18

Cypress Semiconductor

390.16 KB

1.8v synchronous pipelined sram.

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