CY7C1311AV18 - (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.
QDR-II architecture consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data
CY7C1311AV18 Features
* Separate Independent Read and Write Data Ports
* Supports concurrent transactions
* 250-MHz Clock for High Bandwidth
* 4-Word Burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 M
