CY7C1311JV18 - (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture.
QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.
The read port has dedicated data outputs to support
CY7C1311JV18 Features
* CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 ® Configurations CY7C1311JV18
* 2M x 8 CY7C1911JV18
* 2M x 9 CY7C1313JV18
* 1M x 18 CY7C1315JV18
* 512K x 36 Separate Independent Read and Write Data Ports
* Supports concurrent transactions 300 MHz Cloc
