CY7C1319BV18 - 1.8V Synchronous Pipelined SRAM
* 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) * 300-MHz clock for high bandwidth * 4-Word burst for reducing address bus frequency * Double Data Rate (DDR) interfaces (data transferred at 600MHz) @ 300 MHz * Two input clocks (K and K) for precise DDR
