CY7C1420KV18
Features
- 36-Mbit density (2M × 18, 1M × 36)
- 333 MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Synchronous internally self-timed writes
- DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH
- Operates similar to DDR-I device with 1 cycle read latency when DOFF is asserted LOW
- 1.8 V core power supply with HSTL inputs and outputs
- Variable drive HSTL output buffers
- Expanded HSTL output voltage (1.4 V to VDD)
- Supports both 1.5 V and 1.8 V IO supply
- Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
- Offered in both Pb-free and non Pb-free packages
- JTAG 1149.1 patible test access port
- Phase...
