CY7C1420KV18 architecture equivalent, 36-mbit ddr ii sram two-word burst architecture.
* 36-Mbit density (2M × 18, 1M × 36)
* 333 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) inter.
The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are .
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