Description
The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture..
Features
- 36-Mbit density (2M × 18, 1M × 36).
- 333 MHz clock for high bandwidth.
- Two-word burst for reducing address bus frequency.
- Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz.
- Two input clocks (K and K) for precise DDR timing.
- SRAM uses rising edges only.
- Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches.
- Echo clocks (CQ and CQ) simplify data capture in high speed
systems.
- Synchronous in.
