digital fet/ dual p-channel.
-25 V, -0.12 A continuous, -0.5 A Peak. R DS(ON) = 13 Ω @ VGS= -2.7 V R DS(ON) = 10 Ω @ VGS = -4.5 V. Very low level gate drive requirements allowing direct operation in .
as a replacement for digital transistors in load switchimg applications. Since bias resistors are not required this one .
These Dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This dev.
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