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Hanbit Electronics

HMN1M8D Datasheet Preview

HMN1M8D Datasheet

Non-Volatile SRAM MODULE 8Mbit

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HANBit
HMN1M8D
Non-Volatile SRAM MODULE 8Mbit (1,024K X 8-Bit), 36Pin-DIP, 5V
Part No. HMN1M8D
GENERAL DESCRIPTION
The HMN1M8D Nonvolatile SRAM is a 8,388,608-bit static RAM organized as 1,048,576 bytes by 8 bits.
The HMN1M8D has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write
cycles of standard SRAM and integral control circuitry which constantly monitors the single 5V supply for an out-of-
tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the
memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the
SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is
switched on to sustain the memory until after VCC returns valid.
The HMN1M8D uses extremely low standby current CMOS SRAMs, coupled with small lithium coin cells to provide non-
volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w Access time : 70, 85, 120, 150 ns
w High-density design : 8Mbit Design
w Battery internally isolated until power is applied
w Industry-standard 36-pin 1,024K x 8 pinout
w Unlimited write cycles
w Data retention in the absence of VCC
w 10-years minimum data retention in absence of power
w Automatic write-protection during power-up/power-down
cycles
w Data is automatically protected during power loss
OPTIONS
w Timing
70 ns
85 ns
120 ns
150 ns
MARKING
- 70
- 85
-100
-150
PIN ASSIGNMENT
NC 1
NC 2
A18 3
A16 4
A14 5
A12 6
A7 7
A6 8
A5 9
A4 10
A3 11
A2 12
A1 13
A0 14
DQ0 15
DQ1 16
DQ2 17
VSS 18
36 VCC
35 A19
34 NC
33 A15
32 A17
31 /WE
30 A13
29 A8
28 A9
27 A11
26 /OE
25 A10
24 /CE
23 DQ7
22 DQ6
21 DQ5
20 DQ4
19 DQ3
36-pin Encapsulated Package
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
1 HANBit Electronics Co.,Ltd




Hanbit Electronics

HMN1M8D Datasheet Preview

HMN1M8D Datasheet

Non-Volatile SRAM MODULE 8Mbit

No Preview Available !

HANBit
HMN1M8D
FUNCTIONAL DESCRIPTION
The HMN1M8D executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the
address inputs(A0-A19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the eight
data output drivers within tACC (access time) after the last address input signal is stable.
When power is valid, the HMN1M8D operates as a standard CMOS SRAM. During power-down and power-up cycles, the
HMN1M8D acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
The HMN1M8D is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs
are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE
must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The /OE control
signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled
(/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge.
The HMN1M8D provides full functional capability for Vcc greater than 4.5 V and write protects by 4.37 V nominal. Power-
down/power-up control circuitry constantly monitors the Vcc supply for a power-fail-detect threshold VPFD. When VCC falls
below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become dont careand
all outputs are high impedance. As Vcc falls below approximately 3 V, the power switching circuit connects the lithium
energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 3.0 volts, the power switching
circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after Vcc exceeds 4.5 volts.
BLOCK DIAGRAM
PIN DESCRIPTION
/OE
2 x 512K x 8
A0-A18
/WE
SRAM
Block
DQ0-DQ7
Power
/CE CON
/CE
Power Fail
VCC
A19 Control
Lithium
Cell
A0-A19 : Address Input
/CE : Chip Enable
VSS : Ground
DQ0-DQ7 : Data In / Data Out
/WE : Write Enable
/OE : Output Enable
VCC: Power (+5V)
NC : No Connection
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
2 HANBit Electronics Co.,Ltd


Part Number HMN1M8D
Description Non-Volatile SRAM MODULE 8Mbit
Maker Hanbit Electronics
Total Page 9 Pages
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