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  Holtek Semiconductor Electronic Components Datasheet  

HT24LC64 Datasheet

CMOS 64K 2-WIRE SERIAL EEPROM

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HT24LC64
www.DataSheet4U.cAombsolute Maximum Ratings
Operating Temperature (Commercial) ........................................................................................................ 0°C to 70°C
Storage Temperature ............................................................................................................................ -50°C to 125°C
Applied VCC Voltage with Respect to VSS .................................................................................VSS -0.3V to VSS+6.0V
Applied Voltage on any Pin with Respect to VSS ................................................................................................VSS -0.3V to VCC+0.3V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Symbol
Parameter
VCC Operating Voltage
Test Conditions
VCC Conditions
¾¾
Min.
2.4
ICC1 Operating Current
5V Read at 100kHz
¾
ICC2 Operating Current
5V Write at 100kHz
¾
VIL Input Low Voltage
¾¾
-1
VIH
VOL
ILI
ILO
ISTB1
ISTB2
CIN
Input High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Standby Current
Standby Current
Input Capacitance (See Note)
¾¾
2.4V IOL=2.1mA
5V VIN=0 or VCC
5V VOUT=0 or VCC
5V VIN=0 or VCC
2.4V VIN=0 or VCC
¾ f=1MHz 25°C
0.7VCC
¾
¾
¾
¾
¾
¾
COUT Output Capacitance (See Note) ¾ f=1MHz 25°C
¾
Note: These parameters are periodically sampled but not 100% tested.
Ta=0°C to 70°C
Typ.
Max.
Unit
¾ 5.5 V
¾ 2 mA
¾ 5 mA
¾ 0.3VCC V
¾ VCC+0.5 V
¾ 0.4 V
¾ 1 mA
¾ 1 mA
¾ 5 mA
¾ 4 mA
¾ 6 pF
¾ 8 pF
A.C. Characteristics
Ta=0°C to 70°C
Symbol
Parameter
Remark
Standard Mode* VCC=5V±10%
Min. Max. Min. Max.
fSK Clock Frequency
¾ ¾ 100 ¾ 400
tHIGH Clock High Time
¾ 4000 ¾ 600 ¾
tLOW Clock Low Time
¾ 4700 ¾ 1200 ¾
tR SDA and SCL Rise Time Note
¾ 1000 ¾
300
tF SDA and SCL Fall Time
Note
¾ 300 ¾ 300
tHD:STA START Condition Hold Time
After this period, the first
clock pulse is generated.
4000
¾
600
¾
tSU:STA
START Condition Setup Time
Only relevant for repeated
START condition.
4000
¾
600
¾
tHD:DAT Data Input Hold Time
¾ 0¾0¾
tSU:DAT Data Input Setup Time
¾ 200 ¾ 100 ¾
tSU:STO STOP Condition Setup Time
¾ 4000 ¾ 600 ¾
tAA Output Valid from Clock
¾
¾ 3500 ¾
900
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 1.00
2 January 5, 2005


  Holtek Semiconductor Electronic Components Datasheet  

HT24LC64 Datasheet

CMOS 64K 2-WIRE SERIAL EEPROM

No Preview Available !

HT24LC64
www.DataSheet4U.com
Symbol
Parameter
Remark
Standard Mode* VCC=5V±10%
Min. Max. Min. Max.
tBUF Bus Free Time
Time in which the bus must
be free before a new trans- 4700 ¾ 1200 ¾
mission can start
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time
¾ 100 ¾
50
tWR Write Cycle Time
¾ ¾5¾5
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.4V to 5.5V
For relative timing, refer to timing diagrams
Unit
ns
ns
ms
Functional Description
· Serial clock (SCL)
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
· Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open drain driven and may be wired-OR
with any number of other open drain or open collector
devices.
· A0, A1, A2
The A2, A1 and A0 pins are device address inputs that
are hard wired or left not connected for hardware com-
patibility with HT24LC64. When the pins are hard-
wired, as many as eight 64K devices may be
addressed on a single bus system (device addressing
is discussed in detail under the Device Addressing
section). These inputs must be tied to VCC or VSS, to
establish the device select code.
· Write protect (WP)
The HT24LC64 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when the connection is
grounded. When the write protect pin is connected to
VCC, the write protection feature is enabled and oper-
ates as shown in the following table.
WP Pin Status
Protect Array
At VCC
At VSS (floating)
Full Array (64K)
Normal Read/Write Operations
Memory Organization
Internally organized with 8192 8-bit words, the 64K re-
quires a 13-bit data word address for random word ad-
dressing.
Device Operations
· Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
· Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
· Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
· Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
cycle.
D a ta a llo w e d
to c h a n g e
SDA
SCL
S ta rt A d d re s s o r
c o n d itio n a c k n o w le d g e
v a lid
N o A C K S to p
s ta te c o n d itio n
Device Addressing
The 64K EEPROM devices require an 8-bit device ad-
dress word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
The 64K EEPROM uses the three device address bits
A2, A1, A0 to allow as many as eight devices on the
same bus. These bits must compare to their corre-
sponding hardwired input pins.
Rev. 1.00
3 January 5, 2005


Part Number HT24LC64
Description CMOS 64K 2-WIRE SERIAL EEPROM
Maker Holtek Semiconductor
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