HY5DU281622AT-6 Datasheet | SK Hynix

description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3/May. 02 1 Revision History 1. Revision 0.2 (Dec. 01) 1) Separated ‘Function description ’ and ‘Timing diagram’ parts - These are available in Web site (.hynix.) 2. Revision 0.3 (May. 02) 1) Input leakage current changed from +/-5u A to +/-2u A Rev. 0.3/May. 02 HY5DU281622AT-6 DESCRIPTION The Hynix HY5DU281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are patible with SSTL_2. FEATURES - - - - - - - - VDD, VDDQ = 2.5V +/- 5% All inputs and outputs are patible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe - - - - - - - - All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Write mask byte controls by LDM and UDM Programmable /CAS Latency 3 supported Programmable Burst Length 2 / 4 / 8 with both sequential and...