HY5DU281622AT-6
Key Features
- VDD, VDDQ = 2.5V +/- 5% All inputs and outputs are patible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe
- All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Write mask byte controls by LDM and UDM Programmable /CAS Latency 3 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Internal 4 bank operations with single pulsed /RAS Auto refresh and self refresh supported 4096 refresh cycles / 64ms Full and Half strength driver option controlled by EMRS
